Lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In such a case, the mask may contain a circuit pattern corresponding to an individual layer of the IC, and this pattern can be imaged onto a target portion (e.g., comprising one or more dies) on a substrate (silicon wafer) that has been coated with a layer of radiation-sensitive material (resist). In general, a single wafer will contain a whole network of adjacent target portions that are successively irradiated via the projection system, one at a time. In one type of lithographic projection apparatus, each target portion is irradiated by exposing the entire mask pattern onto the target portion in one go; such an apparatus is commonly referred to as a wafer stepper. In an alternative apparatus, commonly referred to as a step-and-scan apparatus, each target portion is irradiated by progressively scanning the mask pattern under the projection beam in a given reference direction (the “scanning” direction) while synchronously scanning the substrate table parallel or anti-parallel to this direction. Since, in general, the projection system will have a magnification factor M (generally >1), the speed V at which the substrate table is scanned will be a factor M times that at which the mask table is scanned. More information with regard to lithographic devices as described herein can be gleaned, for example, from U.S. Pat. No. 6,046,792, incorporated herein by reference.
In a manufacturing process using a lithographic projection apparatus, a mask pattern is imaged onto a substrate that is at least partially covered by a layer of radiation-sensitive material (resist). Prior to this imaging step, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures, such as a post-exposure bake (PEB), development, a hard bake and measurement/inspection of the imaged features. This array of procedures is used as a basis to pattern an individual layer of a device, e.g., an IC. Such a patterned layer may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemo-mechanical polishing, etc., all intended to finish off an individual layer. If several layers are required, then the whole procedure, or a variant thereof, will have to be repeated for each new layer. Eventually, an array of devices will be present on the substrate (wafer). These devices are then separated from one another by a technique such as dicing or sawing, whence the individual devices can be mounted on a carrier, connected to pins, etc.
For the sake of simplicity, the projection system may hereinafter be referred to as the “optics;” however, this term should be broadly interpreted as encompassing various types of projection systems, including refractive optics, reflective optics, and catadioptric systems, for example. The radiation system may also include components operating according to any of these design types for directing, shaping or controlling the projection beam of radiation, and such components may also be referred to below, collectively or singularly, as a “lens.” Further, the lithographic apparatus may be of a type having two or more substrate tables (and/or two or more mask tables). In such “multiple stage” devices the additional tables may be used in parallel, or preparatory steps may be carried out on one or more tables while one or more other tables are being used for exposures. Twin stage lithographic apparatus are described, for example, in U.S. Pat. No. 5,969,441, incorporated herein by reference.
The photolithographic masks referred to above comprise geometric patterns corresponding to the circuit components to be integrated onto a silicon wafer. The patterns used to create such masks are generated utilizing CAD (computer-aided design) programs, this process often being referred to as EDA (electronic design automation). Most CAD programs follow a set of predetermined design rules in order to create functional masks. These rules are set by processing and design limitations. For example, design rules define the space tolerance between circuit devices (such as gates, capacitors, etc.) or interconnect lines, so as to ensure that the circuit devices or lines do not interact with one another in an undesirable way. A critical dimension of a circuit can be defined as the smallest width of a line or hole or the smallest space between two lines or two holes. Thus, the CD determines the overall size and density of the designed circuit.
As the required CDs continue to decrease, photolithographic simulation based on physical models has become an essential tool for understanding and optimizing the advanced photolithographic processes necessary for today's advanced circuit designs. An important aspect of such simulation processes is to utilize calibrated models which accurately describe the resist process (e.g., the image to be formed in the resist layer deposited on the substrate). This is especially true in the low-k1 regime where the printed images in photoresist depart significantly from the projected optical image. Reasons for this disparity are well understood and relate to diffusion of components in the photoresist and finite dissolution contrast. As such, without calibration of the photoresist model to match experimental data, the utility of photolithographic simulation processes are significantly reduced. A characteristic of a well calibrated model is that the critical dimensions (CD) of printed features are accurately predicted.
Recently though it has become clear that current simulation models may be insufficient as many low-k1 processes are limited not by details of the measured and predicted CDs, but by other considerations such as the roughness of the printed feature and whether it actually appears on the wafer or has suffered some type of pattern failure. Line width roughness (LWR), which is defined as the 3σ variation in the measured feature width, has received significant attention because as feature sizes and k1 simultaneously shrink, this width variation can be an appreciable fraction of the total CD budget, and device performance can be compromised as a result of LWR.
Currently, however, generally speaking LWR and pattern failure cannot be readily predicted by standard photolithographic simulation tools, and in fact, their prediction is typically not even addressed. Models for calculating microscopic roughness, specifically line width roughness (LWR) have appeared in the literature, but these known techniques are slow and complex and cannot be easily incorporated into the standard method of working with simulators, and therefore do not offer a practical solution.
Accordingly, there exists a need for a method for predicting both LWR and pattern failure that is both practical and efficient and which can be readily implemented into current photolithography simulation processes.